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CMX639
Consumer / Commercial CVSD Digital Voice Codec
D/639/2 November 2000 Provisional Issue
Features
*
Applications
* *
*
Single Chip Full Duplex CVSD codec * Integrated Input and Output Filters * Robust Coding for Wireless Links * Programmable Sampling Clocks * 3 and 4 bit Companding Algorithms Low Power/Small Size for Portable Devices * 1.9mA/2.75mA typ. @ 3.0V/5.0V * 3.0V to 5.5V Operation * Powersave Mode
* *
Consumer and Business Handheld Devices Digital Voice Appliances * Spread Spectrum Wireless * Cordless Phones * Voice Recording and Storage * Delay Lines Time Domain Scramblers Multiplexers and Switches
1.1
Brief Description
The CMX639 is a Continuously Variable Slope Delta Modulation (CVSD) full duplex CODEC for use in consumer and commercial digital voice communication systems. With its robust and selectable coding algorithms, low cost, very low power, and small size, the CMX639 is ideal for use in a wide variety of consumer and business digital voice applications. Its completely integrated CODEC simplifies design and eliminates the costs, complexity and risk of external filters and software algorithms. 8kbps to 128kbps data/sampling clock rates are supported both via external clock signals or internally generated, programmable clocks. Internal data/sampling clocks are derived from an on-chip reference oscillator that uses an external clock crystal. An internal data/sampling clock output signal is provided to synchronize external circuits, if desired. Multiplexer applications are also well supported by the encoder output's three-state/high impedance enable feature. The CMX639 operates from 2.7V to 5.5V supplies and is available in the following packages: 24-pin TSSOP (CMX639E2), 16-pin SOIC (CMX639D4) and 22-pin PDIP (CMX639P6).
(c) 2000 Consumer Microcircuits Limited
CVSD Codec
CMX639
CONTENTS Section 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Page Features and Applications ..................................................................1 Brief Description ..................................................................................1 Block Diagram......................................................................................3 Signal List ............................................................................................4 External Components ..........................................................................6 General Description.............................................................................7 Application Notes ................................................................................7 Performance Specification ..................................................................8 1.7.1 Electrical Performance...............................................................8 1.7.2 Packaging ...............................................................................15
(c) 2000 Consumer Microcircuits Limited
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CMX639/2
CVSD Codec
CMX639
1.2
Block Diagram
Figure 1 Block Diagram
(c) 2000 Consumer Microcircuits Limited
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CMX639/2
CVSD Codec
CMX639
1.3
P6 22-pin PDIP
Signal List
E2 24-pin TSSOP D4 16-pin SOIC
Signal Name Xtal/Clock
Type input
Description Input to the clock oscillator inverter. A 1.024MHz Xtal input or externally derived clock is injected here. No Connection The 1.024 MHz output of the clock oscillator inverter. No Connection A logic I/O port. External encode clock input or internal data clock output. Clock frequency is dependent upon Clock Mode 1 and 2 inputs and Xtal frequency. Note: No internal pull-up is provided. See Table 3. The encoder digital output. This is a three-state output whose condition is set by the Data Enable and Powersave inputs. See Table 2. When this pin is at a logical '0' the encoder is forced to an idle state and the encoder digital output is `0101...', a perfect idle pattern. When this pin is a logical '1' the encoder encodes as normal. Internal 1M pull-up. Data is made available at the encoder output pin by control of this input. See Encoder Output pin. Internal 1 M pull-up. No Connection Normally at VDD/2, this pin should be externally decoupled by capacitor C4. Internally pulled to VSS when Powersave is a logical '0'. The analog signal input. Internally biased at VDD/2, this input requires an external coupling capacitor. The source impedance driving the coupling capacitor should be less than 1k. A lower driving source impedance will reduce encoder output channel noise levels. Negative Supply No Connection The recovered analog signal is output at this pin. It is the buffered output of a lowpass filter and requires external components. During `Powersave' this output is open circuit. No Connection
1
1
1
2 3 4
2 3 4 5
N/C 2
Xtal
output
3
N/C Encoder Data Clock
input/ output
5
6
4
Encoder Output
output
6
7
Not present
Encoder Force Idle input
7
8
5
Data Enable
input
8 9
9 10
6
N/C VBIAS
10
11
7
Encoder Input
input
11 12 13
12 13 14
8 9
VSS N/C Decoder Output
power output
14
15
N/C
(c) 2000 Consumer Microcircuits Limited
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CMX639/2
CVSD Codec
CMX639
P6 22-pin PDIP
E2 24-pin TSSOP
D4 16-pin SOIC
Signal Name
Powersave
Type Input
Description A logic '0' at this pin puts most parts of the codec into a quiescent, non-operational state. When at a logical '1', the codec operates normally. Internal 1 M pull-up. No Connection A logic '0' at this pin gates a `0101...' pattern internally to the decoder so that the Decoder Output goes to VDD/2. When this pin is a logical '1' the decoder operates as normal. Internal 1M pull-up. The received digital signal input. Internal 1 M pull-up. A logic I/O port. External decode clock input or internal data clock output. Clock frequency is dependent upon Clock Mode 1 and 2 inputs and Xtal frequency. Note: No internal pull-up is provided. See Table 3. A logic '1' at this pin sets this device for a 3-bit companding algorithm. A logical '0' sets a 4-bit companding algorithm. Internal 1 M pull-up. Clock rates refer to f = 1.024MHz Xtal/Clock input. During internal operation the data clock frequencies are available at these ports for external circuit synchronization. Independent or common data rate inputs to Encode and Decode data clock ports may be employed in the External Clocks mode. Internal 1M pull-ups. See Table 3. Positive Supply. A single 3.0V to 5.5V supply is required. This pin should be externally decoupled to VSS by capacitor C5.
15
16
10
16
17 18
N/C
Not present
Decoder Force Idle input
17 18
19 20
11 12
Decoder Input Decoder Data Clock
input input/ output
19
21
13
Algorithm
input
20
22
14
Clock Mode 2
input
21
23
15
Clock Mode 1
input
22
24
16
VDD
power
(c) 2000 Consumer Microcircuits Limited
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CMX639/2
CVSD Codec
CMX639
1.4
External Components
Figure 2 Recommended External Connections R1 C1 C2 C3 Note 1 Note 2 Note 2 Note 3 1M 33pF 33pF 1.0F
10% 20% 20% 20%
C4 C5 X1
Note 4 Note 5 Note 6, 7
1.0F 1.0F 1.024MHz
20% 20%
Table 1 Recommended External Components Notes: 1. Oscillator inverter bias resister 2. Xtal circuit load capacitor 3. The drive source impedance connected to the coupling capacitor's input node, rather than the CMX639 ENCODER INPUT pin node, should be should be less than 1k. Output idle channel noise levels will improve with even lower source impedances driving the coupling capacitor's input node. 4. Bias decoupling capacitor 5. VDD decoupling capacitor 6. A 1.024MHz Xtal/Clock input will yield exactly 16kbps/32kbps/64kbps internally generated data clock rates 7. For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of VDD, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain crystal oscillator design assistance, please consult your crystal manufacturer.
(c) 2000 Consumer Microcircuits Limited
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CMX639/2
CVSD Codec
CMX639
1.5
General Description
Data Enable 1 0 1
Powersave
Encoder Output Enable High Z (open circuit) VSS
1 don't care 0
Table 2 Encoder Output
Clock Mode 1 0 0 1 1
Clock Mode 2 0 1 0 1
Data/Sampling Clock Rate (CLOCK/XTAL = f = 1.024MHz) External Clocks Internally generated @ f/16 Internally generated @ f/32 Internally generated @ f/64 Table 3 Clock Modes and Pins
Example for f = 1.024MHz External Clocks Internally generated @ 64kbps Internally generated @ 32kbps Internally generated @ 16kbps
1.6
Application Notes
Figure 3 System Configuration using the CMX639
(c) 2000 Consumer Microcircuits Limited
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CMX639/2
CVSD Codec
CMX639
1.7
1.7.1
Performance Specification
Electrical Performance
1.7.1.1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. Min. -0.3 -0.3 -30 -20 Max. 7.0 VDD + 0.3 +30 +20 Units V V mA mA
Supply (VDD - VSS) Voltage on any pin to VSS Current into or out of VDD and VSS pins Current into or out of any other pin
P6 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature
Min.
-40 -40
Max. 800 10 +125 +85
Units mW mW/C C C
E2 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature
Min.
-40 -40
Max. 300 3.0 +125 +85
Units mW mW/C C C
D4 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature
Min.
-40 -40
Max. 800 10 +125 +85
Units mW mW/C C C
1.7.1.2 Operating Limits Correct operation of the device outside these limits is not implied. Notes Supply (VDD - VSS) Operating Temperature Xtal Frequency Min. 2.7 -40 0.500 Max. 5.5 +85 2.048 Units V C MHz
(c) 2000 Consumer Microcircuits Limited
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CMX639/2
CVSD Codec
CMX639
1.7.1.3 Operating Characteristics For the following conditions unless otherwise specified: Xtal Frequency = 1.024 MHz, Sample Clock Rate = 32 kbps, Audio Test Frequency = 820 Hz, VDD = 3.0V to 5.5V, Tamb = - 40C to +85C, Audio Level 0dB ref (0dBm0) = 489mV rms. Static Values IDD (powersaved) IDD (enabled) @ VDD = 3.0V IDD (enabled) @ VDD = 5.0V Input Logic `1' Input Logic `0' Output Logic `1' Output Logic `0' Digital Input Impedance Logic I/O pins Logic Input pins, Pull-up Resistor Digital Output Impedance Analog Input Impedance Analog Output Impedance Three State Output Leakage Insertion Loss Notes 6 6 6 Min. Typ. 600 1.90 2.75 Max. Units A mA mA V V V V M k k k A dB
70% VDD 30% VDD 80% VDD 20% VDD 1.0 300 4.0 2 100 800 3
4 0
1
(c) 2000 Consumer Microcircuits Limited
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CMX639/2
CVSD Codec
CMX639
Dynamic Values Encoder: Analog Signal Input Levels VDD = 3.0V VDD = 5.0V Principal Integrator Frequency Encoder Passband Compand Time Constant Decoder: Analog Signal Output Levels VDD = 3.0V VDD = 5.0V Decoder Passband Encoder Decoder (Full Codec): Passband Stopband Stopband Attenuation Passband Gain Passband Ripple Output Noise (Input Short Circuit) Perfect Idle Channel Noise (Encode Forced) Group Delay Distortion (1000Hz - 2600Hz) (600Hz - 2800Hz) (500Hz - 3000Hz) Xtal/Clock Frequency
Notes
Min.
Typ.
Max.
Units
7 7 4
-37 -33 160 3240 5
6 10
dB dB Hz Hz ms
7 7 4 4
-37 -33 3200 300 6 60 0 -3.0
6 10
dB dB Hz Hz kHz dB dB dB dBm0p dBm0p
3400 10
3.0 -60 -63 450 750 1500 2.048
8 8, 9 5
10, 11
0.500
1.024
s s s MHz
Notes: 1. All logic inputs except Encoder and Decoder Data clocks. 2. The source impedance driving the coupling capacitor should be less than 1k. A lower driving source impedance will reduce encoder output channel noise levels. 3. For an Encoder/Decoder combination. 4. See Figure 5. 5. Group Delay Distortion for the full codec is relative to the delay with an 820Hz, -20dB signal at the encoder input. 6. Not including any current drawn from the device pins by external circuits. 7. Recommended values. 8. dBm0p units are measured after the application of a psophometrically weighted filter that is commonly applied in voice communication applications per CCITT Recommendation G.223. 9. Forced idle encode/decode control not available on D4 (16-pin SOIC) package.
10. Some applications may benefit from the use of an Xtal/Clock frequency other than 1.024MHz. Note: Codec time constants and filter response curves are effectively proportional to Xtal/Clock frequency
(c) 2000 Consumer Microcircuits Limited
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CMX639/2
CVSD Codec
CMX639
and so will shift with the use of Xtal/Clock frequencies other than 1.024MHz. For example, the specified Encoder Decoder (Full Codec) passband of 300Hz min. to 3400Hz max. for a 1.024MHz Xtal/Clock will shift to 600Hz min. to 6800Hz max. when the device is operated from a 2.048MHz Xtal/Clock. For this reason, all CMX639 codecs involved in the same communications link should usually be operated from the same Xtal/Clock frequency. Example 1: A design saves the cost of a 1.024MHz Xtal or clock generator by making use of an already existing clock source of a frequency other than 1.024MHz. Example 2: Best noise performance is achieved when the CMX639 codec data clock is internally generated. If a codec bit rate other than 16kbps, 32kbps or 64kbps is desired then an Xtal/Clock different from 1.024MHz can be used to proportionately shift the available set of internally generated clock rates, as needed. Example 3: To increase the codec high frequency response and audio bandwidth a faster Xtal/Clock speed can be used. Other designs may prefer the proportionately higher codec bandwidths and data rates that can be supported with faster clock speeds. 11. In general, optimum codec performance is achieved when both encoder and decoder Xtal/Clock signals are synchronized. While this is practical in many telecom applications, it may not be so for others such as wireless data links. The CMX639 decoder can generally deliver best performance when its data clock is recovered/derived from the received data stream and applied as an external data clock to the decoder as per the decoder timing depicted in Figure 4. Nonetheless, some Xtal/Clock frequency and data rate combinations are better served by the use of internal clocks. Experimentation with each specific design may provide the best guidance for making this design choice.
(c) 2000 Consumer Microcircuits Limited
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CMX639/2
CVSD Codec
CMX639
1.7.1.3 Operating Characteristics (continued) Timing Diagram
ENCODER TIMING
ENCODER CLOCK
tCH
DATA CLOCKED
tIF
tCL
tCH tIR
ENCODER DATA OUTPUT
tPCO
DECODER CLOCK
DECODER TIMING
DATA CLOCKED
DECODER DATA INPUT
tSU
tH
DATA TRUE TIME
MULTIPLEXING FUNCTION
ENCODER OUTPUT
HIGH Z HIGH Z
tDR
DATA ENABLE
tDF
Figure 4 Serial Bus Timing For the following conditions unless otherwise specified: Xtal Frequency = 1.024 MHz, VDD = 3.0V to 5.0V, Tamb = - 40C to +85C. Serial Bus Timing (ref. Figure 4) tCH tCL tIR tIF tSU tH tSU +tH tPCO tDR tDF Clock 1 pulse width Clock 0 pulse width Clock rise time Clock fall time Data set-up time Data hold time Data true time Clock to output delay time Data rise time Data fall time 600 1.5 750 100 100 Notes Min. 1.0 1.0 0 100 100 450 Typ. Max. Units
s s
ns ns ns ns
s
ns ns ns
(c) 2000 Consumer Microcircuits Limited
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CMX639/2
CVSD Codec
CMX639
1.7.1.3 Operating Characteristics (continued) Typical Codec Performance
0
C o d e c G a in in c lu d in g e n c o d e a n d d e co d e , (d B )
Input Level = -15dBmO Data Clocks = 32kbps Xtal = 1.024MHz
-10 -20 -30 -40 -50 -60 1 2 3 Frequency (kHz) 4 5 6
Figure 5 Typical Frequency Response (32kbps)
35
Input Level = -20dB
30
64kb/s
25
S /N (dB )
20 32kb/s 15
10 16kb/s 5 500 1000 1500 2000 2500 3000 3500
Frequency (Hz)
Figure 6 Typical S/N Ratio with Input Frequency
(c) 2000 Consumer Microcircuits Limited
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CMX639/2
CVSD Codec
CMX639
3
Input Frequency = 820Hz
35
Ref: 0dB Input Level = 489mVrms Input Frequency = 820 Hz
A tten u ation (dB ) ref @ -15d B m O
2 1 0 -1 -40 -30 -20 -10 0 10 Input Level (dBmO)
30 S /N (dB )
64 kbps
32 kbps
20
16 kbps 10 -40 -30 -20 -10 Input Level (dB) ref. 0
Figure 7 Typical Variation of Gain with Input Level (32kbps)
Figure 8 Typical S/N Ratio with Input Level
(c) 2000 Consumer Microcircuits Limited
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CMX639/2
CVSD Codec
CMX639
1.7.2
Packaging
Figure 9 P6 Mechanical Outline: Order as part no. CMX639P6
Figure 10 E2 Mechanical Outline: Order as part no. CMX639E2
(c) 2000 Consumer Microcircuits Limited
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CMX639/2
CVSD Codec
CMX639
Figure 9 D4 Mechanical Outline: Order as part no. CMX639D4
Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.
Oval Park - LANGFORD MALDON - ESSEX CM9 6WG - ENGLAND
Telephone: +44 (0)1621 875500 Telefax: +44 (0)1621 875600 e-mail: sales@cmlmicro.co.uk http://www.cmlmicro.co.uk
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits. These companies are all 100% owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 1996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached.
Company contact information is as below:
CML Microcircuits (UK)Ltd
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (USA) Inc.
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com
4800 Bethania Station Road, Winston-Salem, NC 27105, USA Tel: +1 336 744 5050, 0800 638 5577 Fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/ 06 Mactech Industrial Building, Singapore 349307 Tel: +65 7450426 Fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com
D/CML (D)/1 February 2002

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